Questionnaire

Objectives: The technical goals are to reduce the transistor size deep into the nano-scale, to radically transform the process technologies through the integration of a large number of new materials, and to master the design technologies for achieving competitive systems-on-chip and systems-in-package with increasing functionality, performance and complexity. This should be obtained without compromising on reliability, energy consumption and costs of such systems. The aim is also to secure the necessary design skills and stimulate the use of technologies in areas where these are insufficiently used. The work supports, and is in line with the orientations proposed by the Technology Platform on nanoelectronics.
Focus: The SO covers research work on process and device technologies and on design technologies of nanoelectronics integrated circuits.
- For process and device technologies, the focus is on:
1. New materials integration and the related innovative processes to improve miniaturisation, performance, and cost of the next generations of nonconventional silicon-based devices (mid-term and long-term) for generic logics, memories, analogue, RF and high power platforms.
These tasks are to be addressed by means of IPs and/or STREPs enabling strong collaboration and complementarity between academia and industry.
2. Equipment and materials R&D activities (short-term and mid-term) and assessment actions (innovation activities with specific evaluation criteria) for the manufacturing of the next generations of chips. Lithography has already been adequately covered in previous FP6 calls for proposals.
These tasks are to be addressed by means of IPs with strong collaboration between users and suppliers, and significant involvement of SMEs.

Details (Instruments)

Objectives: The technical goals are to reduce the transistor size deep into the nano-scale, to radically transform the process technologies through the integration of a large number of new materials, and to master the design technologies for achieving competitive systems-on-chip and systems-in-package with increasing functionality, performance and complexity. This should be obtained without compromising on reliability, energy consumption and costs of such systems. The aim is also to secure the necessary design skills and stimulate the use of technologies in areas where these are insufficiently used. The work supports, and is in line with the orientations proposed by the Technology Platform on nanoelectronics.
Focus: The SO covers research work on process and device technologies and on design technologies of nanoelectronics integrated circuits.
- Design technologies cover methods, tools and architectures for designing advanced nanoelectronic circuits within economical and technical constraints. The focus is on research for :
1. Mastering the design complexity and increasing the design productivity for system-on-chip (SoC) or system-in-package (SiP). This notably involves work on application and design platforms, Intellectual Property reuse, verification and post-fabrication tests, reconfigurable structures, system-on-chip architectures and design flows.
2. Mastering the technological shortcomings of nanoelectronics such as unreliable device behaviour, dispersion of circuit parameters, parasitic and interconnect effects, and leakage currents.
3. Addressing specific "high value" design and test competences that are essential for the strategic European application areas. These include for example analogue and mixed signal, high frequency and RF circuits, smart power and low power.
The three tasks above are to be addressed by means of IPs and STREPs both with involvement of users. Participation of SMEs is encouraged.

Details (Instruments)

Objectives: The technical goals are to reduce the transistor size deep into the nano-scale, to radically transform the process technologies through the integration of a large number of new materials, and to master the design technologies for achieving competitive systems-on-chip and systems-in-package with increasing functionality, performance and complexity. This should be obtained without compromising on reliability, energy consumption and costs of such systems. The aim is also to secure the necessary design skills and stimulate the use of technologies in areas where these are insufficiently used. The work supports, and is in line with the orientations proposed by the Technology Platform on nanoelectronics.
Focus: The SO covers research work on process and device technologies and on design technologies of nanoelectronics integrated circuits.
In addition there is a need for complementary measures, in particular:
1. Access services supporting academic research on design as well as university education of qualified designers through access to industrial design tools and multi-project wafers. Access services are to be addressed by means of SSAs.
2. Stimulation actions13 aim at increasing the interest of students and improving the quality of education in SoC design. This will be done through IPs that emphasize research carried out by, and training of, students in SoC design.
It is expected that stimulation actions and in particular access services are to a significant extent financed through own resources or receipts from third parties.
3. Use actions14 should promote the integration and use of micro- and nanoelectronics technologies (limited to reconfigurable systems) in SME products and in application and/or geographical areas where these technologies are insufficiently used. They cover awareness actions, the development and evaluation of industrial test cases, and the dissemination of results for replication.
IPs will be the instrument for use actions.

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
1. Heterogeneous technologies and devices for mixed-technology micro/nano systems (eg microfluidic/ICT/micro-nano, bio/ICT/micro-nano, chemical/ICT/micro-nano combined). Activities include research at the boundary and integration between different scientific and engineering disciplines, e.g. the combination of silicon and non-silicon technologies and multi-functional integrated micro/nano systems combining information technology with nano-biology, nano-chemistry and combining micro-fluidics and nano-chemistry.
These tasks are to be addressed through IPs and STREPS.

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
2. Technology for very high density hybrid integration (towards e-grains, e-dust). Research activities are to address a family of integration and interfacing technologies aiming at very high densities, unifying heterogeneous technologies including 3-dimensional vertical integration and very thin technologies. Integration of wireless communication interfaces, antennae, power provision and new functionalities into a very small volume/area is also envisaged.
These tasks are to be addressed through IPs and STREPs.

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
3. Integrating micro/nano devices in various materials and in or on large surfaces. Research activities aim at integrating micro/nano components and devices in different materials. Activities include sensing, actuating, interfacing, power control, processing and intelligent devices added to polymers, to plastics, to textiles, and to very large surfaces and very large area display technology and large area electronics. Research includes interfacing nano-to-nano; nano-to-micro-to-macro components; and connecting nano and micro devices to new materials (including connections to organic molecules, living cells).
These tasks are to be addressed through IPs and STREPs.

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
4. Manufacturing and design of mixed technology-based micro/nano systems. Focus of research activities is on flexible manufacturing and new processes, design and business or service concepts for combining different technologies requiring multi-competencies. In addition to research, service actions supporting academic research, feasibility design, prototyping, training and education through access to advanced tools, multi-project fabrication and design competency are called for.
These tasks are to be addressed through IPs (training with specific evaluation criteria).

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
5. Validation and demonstration of networked micro/nano systems and their use to address problems and opportunities in a holistic manner combining device, system, information management and application competencies. Application sectors emphasized are environment, the home, food and agriculture and healthcare.
These tasks are to be addressed through IPs.

Details (Instruments)

Objectives: To push the limits of integrated micro/nano systems through research on a family of mixed technologies (combining for instance micro-nano-technology, ICT and biotechnology) and integration technologies for very high density or for integrating micro/nano devices in various materials and into large surfaces. Validation and demonstration of maturing silicon-based and polymer-based technologies, manufacturing and design issues are also targeted.

Focus
6. Roadmaps, specific coordination and support activities to prepare for a research agenda and to build the research community in order to define major trends and to address the ICT-bio-micro-nano-technology combined field, their technologies and their applications and emphasizing multidisciplinarity and addressing research and innovation at the boundaries of different sciences.
These tasks are to be addressed through SSAs and CAs.

Details (Instruments)

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