Objectives: The technical goals are to reduce the transistor size deep into the nano-scale, to radically transform the process technologies through the integration of a large number of new materials, and to master the design technologies for achieving competitive systems-on-chip and systems-in-package with increasing functionality, performance and complexity. This should be obtained without compromising on reliability, energy consumption and costs of such systems. The aim is also to secure the necessary design skills and stimulate the use of technologies in areas where these are insufficiently used. The work supports, and is in line with the orientations proposed by the Technology Platform on nanoelectronics.
Focus: The SO covers research work on process and device technologies and on design technologies of nanoelectronics integrated circuits.
- Design technologies cover methods, tools and architectures for designing advanced nanoelectronic circuits within economical and technical constraints. The focus is on research for :
1. Mastering the design complexity and increasing the design productivity for system-on-chip (SoC) or system-in-package (SiP). This notably involves work on application and design platforms, Intellectual Property reuse, verification and post-fabrication tests, reconfigurable structures, system-on-chip architectures and design flows.
2. Mastering the technological shortcomings of nanoelectronics such as unreliable device behaviour, dispersion of circuit parameters, parasitic and interconnect effects, and leakage currents.
3. Addressing specific "high value" design and test competences that are essential for the strategic European application areas. These include for example analogue and mixed signal, high frequency and RF circuits, smart power and low power.
The three tasks above are to be addressed by means of IPs and STREPs both with involvement of users. Participation of SMEs is encouraged.
Details (Instruments)